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SEMICONDUCTOR TECHNICAL DATA
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MPC2605
Integrated Secondary Cache for PowerPCTM Microprocessors
The MPC2605 is a single chip, 256KB integrated look-aside cache with copy-back capability designed for PowerPC applications (MPC603 and MPC604). Using 0.38 m technology along with standard cell logic technology, the MPC2605 integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2 cache with one, two, or four chips on a 64-bit PowerPC bus. * * * * * * * * * * * * * * * * Single Chip L2 Cache for PowerPC 66 MHz Zero Wait State Performance (2-1-1-1 Burst) Four-Way Set Associative Cache Design 32K x 72 Data Memory Array 8K x 18 Tag Array Address Parity Support LRU Cache Control Logic Copy-Back or Write-Through Modes of Operation Copy-Back Buffer for Improved Performance Single 3.3 V Power Supply 5 V Tolerant I/O One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB) Single Clock Operation Compliant with IEEE Standard 1149.1 Test Access Port (JTAG) Supports up to Four Processors in a Shared Cache Configuration High Board Density 25 mm 241 PBGA Package BLOCK DIAGRAM
ZP PACKAGE PBGA CASE 1138-01
COPY-BACK BUFFER
CONTROL RD/WR 60X BUS INTERFACE A27, A28 CONTROLLER AND BUS INTERFACE RD/WR 2K x 18 x 4 TAG RAM 2K x 8 LRU 8K x 72 x 4 DATA RAM DH0 - DH31 DL0 - DL31 DP0 - DP7 WAY SELECT
A0 - A31
COMPARE
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 6 2/26/98
(c) Motorola, Inc. 1998 MOTOROLA
MPC2605 1
PIN ASSIGNMENT
1 A B C D E TA F G H J K L M TT3 N P R T U V W SRESET TDI TDO CPU4 BG CPU4 BR CFG2 CPU BG CLK VSS VSS VSS VDD VDD VDD VSS VSS A28 A31 A10 A7 VSS VDD DH5 DH4 VSS DH3 DH2 VSS DH1 DH0 VSS DP1 DH15 VSS DH14 DH13 DH12 VDD DH10 DH11 DH9 VDD DL1 DL0 DH8 VDD DL4 DL3 DL2 VSS VSS DL6 DL5 VSS VSS DP4 DL7 VSS DL10 DL8 VDD DL12 DL9 DP5 DL14 DL11 VDD VDD DL15 DL13 A27 A30 A11 A8 A5 A3 A1 A0 A26 A29 A12 A9 A6 A4 A2 L2 DBG CPU2 BG 2 ABB CPU3 BG FDN L2 BR CFG4 CPU3 BR CPU2 BR 3 L2 BG 4 DH20 5 6 7 8 9 DH27 DH28 10 11 12 DL19 DL20 DL21 VSS 13 DL22 DL23 VSS VSS 14 DP6 DL24 VSS 15 DL25 DL26 VDD 16 DL27 DL28 VDD 17 DL29 DL31 AP3 AP0 18 DL30 DP7 AP2 L2 FLUSH APE AP1 L2 CI GBL TSIZ2 A13 A16 A17 A21 A23 19
DH19 DH17 DH31 DH29 DH18 DH16 DH30 DH22 VSS VSS DP3 VSS
DH26 DL16 DH25 DL17 DL18 VDD
DH23 DH21 L2 MISS INH CPU3 VDD DBG CPU2 DBG DP2
VSS DH24 VDD VDD
CFG3 APEN TSIZ1 TSIZ0 VSS VSS VDD VDD VDD VSS VDD VDD VSS VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VSS VSS VDD VDD VDD VSS A14 A19 A20 A25 VSS A15 A18 A22 A24
CPU L2 CLAIM NC DBG ARTRY TEA CI CPU BR AACK WT
HRESET DBB PWRDN VDD TT1 TT4 TT0 TT2 TBST TS VDD VDD
L2 L2 UPDATE VSS TAG CLR INH TCK TRST CPU4 DBG CFG0 CFG1 DP0 TMS NC VDD VDD DH7 DH6
TOP VIEW (X-RAY VIEW)
MPC2605 2
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PIN DESCRIPTIONS
Pin Locations 19G, 17H - 19H, 17J - 19J, 17K - 19K, 17L - 19L, 17M - 19M, 17N - 19N, 17P - 19P, 17R - 19R, 18T, 19T, 18U, 19U, 18V, 19V, 18W * 3G 2A AACK ABB I/O I/O I/O O I I/O I Address acknowledge input/output. Used as an input to qualify bus grants. Driven as an output during address tenure initiated by the MPC2605. Address parity. Address parity error. When an address parity error is detected, APE will be driven low one clock cycle after the assertion of TS then High-Z following clock cycle. Address parity enable. When tied low, enables address parity bits and the address parity error bit. Address retry status I/O. Generated when a read or write snoop to a dirty processor cache line has occurred. Configuration inputs. These must be tied to either VDD or VSS. CFG0 CFG1 CFG2 0 0 0 256KB 0 1 0 512KB; A26 = 0 0 1 1 512KB; A26 = 1 1 0 0 1MB; A25 - A26 = 00 1 0 1 1MB; A25 - A26 = 01 1 1 0 1MB; A25 - A26 = 10 1 1 1 1MB; A25 - A26 = 11 CFG3 Snoop Data Tenure Selector 0 Supports snoop data tenure 1 Does not support snoop data tenure AACK Driver Enable 0 Disable AACK driver 1 Enable AACK driver Pin Name A0 - A31 Type I/O Description Address inputs from processor. Can also be outputs for processor snoop addresses. A0 is the MSB. A31 is the LSB.
17C - 19C, 17D 19B 18E 1G 2U 2V 1V 17E 2B
*
AP0 - AP3 APE APEN ARTRY CFG0 CFG1 CFG2 CFG3 CFG4
CFG4
2G 3M 2M 3E 1B 1T 2H 2D 2C 1U 1F 3D 3C
CI CLK CPU BG CPU2 BG CPU3 BG CPU4 BG CPU BR CPU2 BR CPU3 BR CPU4 BR CPU DBG CPU2 DBG CPU3 DBG
I/O I I I I I I I I I I I I
Cache inhibit I/O. Clock input. This must be the same as the processor clock input. CPU bus grant input. MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor configuration as the second CPU BG. MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor configuration as the third CPU BG. MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor configuration as the fourth CPU BG. CPU bus request input. MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor configuration as the second CPU BR. MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor configuration as the third CPU BR. MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor configuration as the fourth CPU BR. CPU data bus grant input from arbiter. MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor configuration as the second CPU DBG. MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor configuration as the third CPU DBG.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
MOTOROLA
MPC2605 3
Pin Locations 2T 11A - 13A, 15A - 18A, 11B - 17B, 11C, 12C, 10U, 11U, 10V - 12V, 14V - 17V, 11W - 17W * 4A - 10A, 4B - 10B, 6C, 10C, 8U, 9U, 3V - 6V, 8V, 9V, 3W -10W * 2J
Pin Name CPU4 DBG DL0 - DL31
Type I I/O
Description MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor configuration as the fourth CPU DBG. Data bus low input and output. DL0 is the MSB. DL31 is the LSB.
DH0 - DH31
I/O
Data bus high input and output. DH0 is the MSB. DH31 is the LSB.
DBB
I/O
Data bus busy. Used as input when processor is master, driven as an output after a qualified L2 DBG when MPC2605 is the bus master. Note: To operate in Fast L2 mode, this pin must be tied high. Data bus parity input and output.
14A, 18B, 5C, 8C, 16U, 7V, 13V, 2W * 1C 19E 1J
DP0 - DP7
I/O
FDN GBL HRESET
I/O O I
Flush done I/O used for communication between other MPC2605 devices. Must be tied together between all MPC2605 parts along with a pullup resistor. Global transaction. Always negated when MPC2604 is bus master. Hard reset input from processor bus. This is an asynchronous input that must be low for at least 16 clock cycles to ensure the MPC2605 is properly reset. For proper initialization, TRST must be asserted before HRESET is asserted. Bus grant input from arbiter. Bus request I/O. Normally used as an output. Secondary cache inhibit sampled, after assertion of TS. Assertion prevents linefill. L2 cache claim output. Used to claim the bus for processor initiated memory operations that hit the L2 cache. L2 CLAIM goes true (low) before the rising edge of CLK following TS true. Because this output is not always driven, a pullup resistor may be necessary to ensure proper system functioning. Data bus grant input. Comes from system arbiter, used to start data tenure for bus operations where MPC2605 is the bus master. Causes cache to write back dirty lines and clears all tag valid bits. Prevents line fills on misses when asserted. Invalidates all tags and holds cache in a reset condition. Cache disable. When asserted, the MPC2605 will not respond to signals on the local bus and internal states do not change. Provides low power mode. Prevents address and data transitions into the RAM array. MPC2605 becomes active 4 s after deassertion. Clock must be externally disabled. Soft reset input from processor bus. Transfer acknowledge status I/O from processor bus. Transfer burst status I/O from processor bus. Used to distinguish between burstable and non-burstable memory operations. Test clock input for IEEE 1149.1 boundary scan (JTAG). Test data input for IEEE 1149.1 boundary scan (JTAG). Test data output for IEEE 1149.1 boundary scan (JTAG). Transfer error acknowledge status input from processor bus. Test mode select for IEEE 1149.1 boundary scan (JTAG).
3A 1D 19D 2F
L2 BG L2 BR L2 CI L2 CLAIM
I I/O I O
2E 18D 3B 2N 3N 3J
L2 DBG L2 FLUSH L2 MISS INH L2 TAG CLR L2 UPDATE INH PWRDN
I I I I I I
1N 1E 3K 2P 1P 1R 1H 3P
SRESET TA TBST TCK TDI TDO TEA TMS
I I/O I/O I I O I I
* See pin diagram (page 2) for specific pin assignment of these bus signals.
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Pin Locations 2R 3L 17F - 19F * 1K, 2K, 1L, 2L, 1M * 3H 4C, 15C, 16C, 9D - 11D, 8H - 10H, 4J, 8J, 9J, 16J, 4K, 8K, 12K, 16K, 4L, 11L, 12L, 16L, 10M - 12M, 3T, 9T - 11T, 17T, 3U, 4U, 15U, 17U 7C, 9C, 13C, 14C, 7D, 8D, 12D, 13D, 4G, 16G - 18G, 4H, 11H, 12H, 16H, 10J - 12J, 9K - 11K, 8L - 10L, 4M, 8M, 9M, 16M, 4N, 16N, 7T, 8T, 12T, 13T, 5U - 7U, 12U - 14U 3F, 3R
Pin Name TRST TS TSIZ0 - TSIZ2 TT0 - TT4 WT VDD
Type I I/O I/O I/O I/O Supply
Description Test reset input for IEEE 1149.1 boundary scan (JTAG). If JTAG will not be used, TRST should be tied low. Transfer start I/O from processor bus (can also come from any bus master on the processor bus). Signals the start of either a processor or bus master cycle. Transfer size I/O from processor bus. Transfer type I/O from processor bus. Write through status input from processor bus. When tied to ground, the MPC2605 will operate in write-through mode only (no copy-back). Power supply: 3.3 V 5%.
VSS
Supply
Ground.
NC
--
No connection: There is no connection to the chip.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation (Note 2) Temperature Under Bias Operating Temperature Storage Temperature Symbol VDD Vin, Vout Iout PD Tbias TJ Tstg Value - 0.5 to + 4.6 - 0.5 to VDD + 0.5 20 -- - 10 to + 85 0 to + 125 - 55 to + 125 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
MOTOROLA
MPC2605 5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(TJ = 20 to + 110C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL(min) = - 2.0 V ac (pulse width 20 ns). Symbol VDD VIH VIL Min 3.135 2.0 - 0.5* Typ 3.3 -- -- Max 3.465 5.5 0.8 Unit V V V
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (High-Z State, Vout = 0 to VDD) AC Supply Current (Iout = 0 mA, All inputs = VIL or VIH, VIL = 0 V, and VIH 3.0 V, Cycle Time = 15 ns, max value assumes a constant burst read hit, with 100% bus utilization, and 100% hit rate) AC Quiescent Current (Iout = 0 mA, All inputs = VIL or VIH, VIL = 0 V and VIH 3.0 V, Cycle Time = 15 ns, All Other Inputs DC) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA Min -- -- -- Max 1.0 1.0 720 Unit A A mA
IQ VOL VOH
-- -- 2.4
195 0.4 --
mA V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Output Capacitance Input/Output Capacitance Symbol Cin Cout CI/O Typ 4 6 8 Max 6 8 10 Unit pF pF pF
PACKAGE THERMAL CHARACTERISTICS
Rating Thermal Resistance Junction to Ambient (Still Air, Test Board with Two Internal Planes) Thermal Resistance Junction to Ambient (200 lfpm, Test Board with Two Internal Planes) Thermal Resistance Junction to Board (Bottom) Thermal Resistance Junction to Case (Top) Symbol RJA RJA RJB RJC Max 26.5 23.2 15.9 6.6 Unit C/W C/W C/W C/W
MPC2605 6
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(TJ = 20 to + 110C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Termination to 1.5 V
AC CLOCK SPECIFICATIONS
Timing Reference MPC2605-66 Min -- 15 1.0 40 -- Max 66.67 -- 2.0 60 150 Unit Ui MHz ns ns % ps 1 1, 2 Notes N
Parameter P Frequency of Operation Clock Cycle Time Clock Rise and Fall Time Clock Duty Cycle Measured at 1.5 V Clock Short-Term Jitter (Cycle to Cycle) NOTES: 1. This parameter is sampled and not 100% tested. 2. Rise and fall times for the clock input are measured from 0.4 to 2.4 V.
,
CLOCK INPUT TIMING DIAGRAM
VM
VIH
VIL VM = Midpoint Voltage (1.5 V)
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MPC2605 7
AC SPECIFICATIONS
Timing Reference MPC2605-66 Min 15 4.5 2 2 2 2 2 -- Max -- -- -- 9 9 -- 12 4 Unit Ui ns ns ns ns ns ns ns s 2 2 2 1 1 2 Notes N
Parameter P Clock Cycle Time Input Setup Time Clock to Input Invalid (Input Hold) Clock to Output Driven Clock to Output Valid Clock to Output Invalid Clock to Output High-Z PWRDN Disable to Recovery

NOTES: 1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V level of the rising edge of the input clock. Both input and output timings are measured at the pin. 2. This parameter is sampled and not 100% tested.
CLK
INPUTS

OUTPUTS

MPC2605 8
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MPC2605 RESPONSE TO 60X TRANSFER ATTRIBUTES
TT0 - TT4 X1X10 X1X10 X1010 X1010 00110 00110 00X10 00110 00010 X0010 X0010 00100 00100 00000 00000 01100 TBST 0 0 1 1 0 0 X 0 1 1 1 X X X X X CI 1 1 0 0 1 1 1 1 1 0 0 X X X X X WT X X X X X 1 0 0 0 X X X X X X X Tag Status Miss Hit Hit Clean Hit Dirty Miss Hit Hit Clean Hit Dirty Hit Dirty Hit Clean Hit Dirty Hit Clean Hit Dirty Hit Clean Hit Dirty Hit MPC2605 Response Line-fill (processor read miss) L2 CLAIM, AACK, TA (processor read hit) Paradox -- Invalidate the line (processor n-cacheable read hit clean line) Paradox -- ARTRY, L2 BR, then write back data, invalidate the line (processor n-cacheable read hit dirty line) Line-fill except right after a snoop hit to processor (processor write miss) L2 CLAIM, AACK, TA except after a snoop hit to processor (processor write hit) Cache update (processor write through WT hit clean) Cache update, clear dirty bit Paradox -- ARTRY, L2 BR, write back data, keep valid, clear dirty bit Paradox -- Invalidate the line (processor n-cacheable write hit clean line) Paradox -- ARTRY, L2 BR, then write back data, invalidate the line (processor n-cacheable SB write hit dirty line) Invalidate tag (flush block address-only) ARTRY, L2 BR, write back data, invalidate tag (flush block address-only) No action (clean block address-only) ARTRY, L2 BR, write back data, reset dirty bit (clean block address-only) Invalidate tag (kill block address-only) 1, 3, 5, 6 5, 6 Notes 1, 2, 3 4
NOTES: 1. If a line fill is going to replace a dirty line and the cast out buffer (COB) is full, the line fill will be cancelled. (Unless the line fill is a write which hits in the COB. In this case, the line fill will occur.) 2. If a burst read misses the cache but hits the COB, the MPC2605 will supply the data from the COB, but not perform a line fill. 3. If ARTRY is asserted during a line fill to replace a dirty line, the line fill will be cancelled, the to-be-replaced line will recover its old tag (valid, dirty, tag field), and the COB goes back to an invalid condition, even if the line fill is a burst write to the line in the COB. 4. If ARTRY is asserted during a read hit, the MPC2605 will abort the process. 5. If a processor burst write occurs right after a snoop write that was a cache hit, the MPC2605 will invalidate the line. If the snoop was a cache miss, the MPC2605 will not perform a write allocate. 6. If a processor burst write occurs right after a snoop read that was a cache hit, the MPC2605 will update the cache and clear the dirty bit. If the snoop was a cache miss, the MPC2605 will perform a write allocate.
MPC2605 RESPONSE TO CHIPSET TRANSFER ATTRIBUTES
TT0 - TT4 00100 X0010 X1110 00100 X0010 X1110 00000 X1010 00000 X1010 0110X 00110 Tag Status Hit Clean Invalidate line MPC2605 Response
Hit Dirty
ARTRY and L2 BR write back data, invalidate line (see Note)
Hit Clean Hit Dirty Hit
No action ARTRY and L2 BR, write back data, reset dirty bit (see Note) Invalidate (kill block)
NOTE: In all snoop push cases, BR is sampled the cycle after the ARTRY window. If BR is asserted in this cycle, L2 BR will be immediately negated and an assertion of L2 BG will be ignored.
TRANSFER ATTRIBUTES GENERATED FOR L2 COPYBACK
TT0 - TT4 00010 TBST 0 CI 1 WT 1
MOTOROLA
MPC2605 9
FUNCTIONAL OPERATION
SYSTEM USAGE AND REQUIREMENTS The MPC2605 is a high-performance look-aside cache for PowerPC systems. A look-aside cache is defined as a cache that resides on the same bus as the processor, the memory controller, the DMA bridge, and the arbiter. The advantage of a look-aside cache is that, when the processor makes a memory request, the cache adds no delay to the memory controller's response time in the event that the request cannot be satisfied by the cache. However, there are certain system requirements that must be met before a look- aside cache can be used. Comprehension of L2 CLAIM Because the memory controller sees every memory request that is issued by the processor, there must be a mechanism for the cache to inform the memory controller that it has detected a cache hit and that it will satisfy the processor 's request. The MPC2605 has a signal called L2 CLAIM that is asserted whenever a cache hit is detected. Any memory controller with which the MPC2605 is to be used must have the ability to monitor this signal. Pipeline Depth The 60X bus allows pipelining of transactions such that a new transaction can be initiated before a previous transaction has fully completed. The level of pipelining that exists on the bus is defined by how many new data transactions have been initiated while the original transaction is still being processed. By this definition the MPC2605 can only work in a one level deep pipeline. In the presence of transactions for which it has asserted L2 CLAIM, the MPC2605 can control the level of pipelining by delaying its assertion of AACK. However, for transactions that it cannot control, the MPC2605 is dependent upon the memory controller to control pipeline depth. Thus, another system requirement for the use of the MPC2605 is the use of a memory controller that only allows one level deep of pipelining on the 60X bus. Bus Mastering Bus mastering is a requirement only for systems which seek to use the MPC2605 as a copyback, as opposed to a write-through, cache. The requirement is that the system arbiter must have the ability to allow the MPC2605 to become a bus master. Specifically, the system arbiter must be able to recognize assertions of L2 BR and must have the ability to assert L2 BG and L2 DBG. These are the only requirements above and beyond what should already exist in a PowerPC system. All other necessary control signals are signals that are required for the processor to communicate with the memory controller, the DMA bridge, and the arbiter. CONFIGURATION PINS The MPC2605 has five configuration pins: CFG0, CFG1, CFG2, CFG3, and CFG4. CFG0 - CFG2 These three configuration pins are used to implement the different cache sizes supported by the MPC2605. 256KB: For a single chip implementation, CFG0, CFG1, and CFG2 should all be tied low. 512KB: This two chip configuration requires both parts to have CFG0 tied low and CFG1 tied high. CFG2 is used as a chip select when it matches the value of A26. Therefore, one device must have CFG2 tied low and the other device must have CFG2 tied high. 1MB: The four chip configuration requires all four devices to have CFG0 tied high. The CFG1, CFG2 vector becomes the chip select when it matches the A25, A26 vector. Therefore, each of the four parts must have a unique value of the CFG[1:2] vector. CFG3 Many core logic chipsets are designed such that the DMA bridge and the memory controller are resident in the same device. In such systems there is internal communication between these two functional units. Bus transactions generated by the DMA bridge are solely for the purpose of keeping the system coherent. They are not explicit requests from memory that have data tenures associated with them. However, some chipsets are designed with the memory controller and the DMA bridge partitioned into different devices. In systems such as these, transactions generated by the DMA bridge are true memory requests that have data tenures associated with them. These are called snoop data tenures. Because these two types of systems are fundamentally different, the MPC2605 must know in which type of system it is resident in order to respond properly to the different types of transactions. For systems that do not have snoop data tenures, CFG3 must be tied high. For systems that do use snoop data tenures, CFG3 must be tied low. CFG4 When the MPC2605 asserts L2 CLAIM to signal to the memory controller that a cache hit has been detected, it is taking control of the address and data tenures of the transaction (see 60X Bus Operation and Memory Coherence). This means that the MPC2605 will assert AACK to end the address tenure, and it will assert TA as needed for the data tenure. If the data bus is idle when a processor request is initiated, the MPC2605 will assert AACK the cycle after TS was asserted. If the data bus is busy when the request is made, the MPC2605 will wait until the outstanding data tenure has completed before asserting AACK. By holding off on the assertion of AACK, the MPC2605 enforces the policy of, at most, two outstanding data transactions at any one time. Tying CFG4 low prevents the MPC2605 from asserting AACK to end transactions for which it has asserted L2 CLAIM. In systems that tie CFG4 low it is necessary for the memory controller to assert AACK for all transactions. This allows the DMA bridge to initiate snoop transactions (as defined later) even when there are two outstanding data transactions. If this type of system is implemented, the arbiter must ensure
MPC2605 10
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that the processor's bus grant is negated once there are two outstanding data transactions. It is expected that most systems will tie CFG4 high. RESET/INITIALIZATION To ensure proper initialization and system functionality, the HRESET pin of the MPC2605 should be connected to the same signal that is used to reset the processor. The TRST signal must be negated before HRESET is negated. When HRESET is negated, the MPC2605 commences an internal initialization sequence to clear all of the valid bits in the cache. The sequence takes approximately 4000 clock cycles. During this time the MPC2605 will not participate in any bus transaction that occurs. All transactions are, however, monitored so that, regardless of when the initialization sequence completes, the MPC2605 is prepared to take action on the next transaction initiated by the processor. At some point after this 4000 cycle sequence, the MPC2605 will detect its first cache hit. At this time the system will experience its first assertion of L2 CLAIM. If the memory controller must be configured via software to comprehend assertions of L2 CLAIM, this configuration operation must have completed by this time. For systems that cannot guarantee that this requirement is met, it is necessary to disable the MPC2605 until such time as this configuration can be guaranteed. Disabling the MPC2605 can be accomplished by asserting L2 UPDATE INH sometime during reset and negating it when it is deemed safe for caching to commence. 60X BUS OPERATION All transactions have what is called an address tenure. An address tenure is a set number of bus cycles during which the address bus and its associated control signals are being used for the transaction at hand. In general, there are two types of transactions. Those that only have address tenures, called address-only transactions. And those that require the use of the data bus and therefore will have a data tenure. These transactions are called data transactions. This section describes how address and data tenures are defined as viewed by the MPC2605. Address Tenures Address tenures on the 60X bus are fairly well defined. They start with an assertion of TS by a device that has been granted the bus by the system arbiter. This device is called the bus master for this transaction. At the same time that TS is asserted, the bus master also drives the address and all other relevant control signals that define the transaction. TS is only asserted for one cycle but all other signals are held valid by the bus master until some other device asserts AACK. The device that asserts AACK becomes the slave to this transaction. Typically, the slave is the memory controller, although for transactions that are cache hits the MPC2605 becomes the slave by driving L2 CLAIM. Transactions can be aborted by any device on the bus by asserting ARTRY. ARTRY may be asserted at any time after TS is asserted, but must be held through the cycle after AACK is asserted. This cycle is referred to as the ARTRY window, since it is the cycle in which all devices sample ARTRY to determine if the address tenure has completed successfully.
If an address tenure is not aborted by an assertion of ARTRY, then the next bus master is free to assert TS, the cycle after the ARTRY window to start a new address tenure. If ARTRY is asserted in the ARTRY window, all devices that are not asserting ARTRY must negate their bus request in the following cycle. This next cycle is called the BR window. The purpose of this protocol is to give immediate bus mastership to the device that asserted ARTRY with the expectation that that device will take this opportunity to clean up whatever circumstances caused it to assert ARTRY. Typically, this involves writing data back to memory to maintain coherence in the system. Data Tenures Data tenures are more complicated to define than address tenures. They require two conditions to start: an assertion of TS that initiates a data transaction and a qualified assertion of the bus master's data bus grant. For a data bus grant to be considered qualified, no device on the bus may be asserting DBB in the cycle that the data bus grant is asserted. Data transactions come in two types: single-beat transactions and burst transactions. The type is determined by the state of TBST during the address tenure of the transaction. If the bus master asserts TBST, the transaction is a burst transaction and will require four assertions of TA in order to complete normally. If TBST is negated during the address tenure, the transaction only requires one assertion of TA, thus the name single-beat. Which device drives the data bus during a data transaction depends upon whether the transaction is a read or a write. For a read transaction, the slave device drives the data bus. For a write transaction, the master drives the data bus. In all data transactions, the slave device asserts TA to indicate that either valid data is present on the bus, in the case of a read; or that it is reading data off the data bus, in the case of a write. The master device asserts DBB the cycle after it has been granted the data bus and keeps it asserted until the data tenure has completed. A data tenure can be aborted in two different ways. The address tenure for the transaction can be aborted by an assertion of ARTRY. Or, the slave device may assert TEA to indicate that some error condition has been detected. Either event will prematurely terminate the data tenure. Data Streaming For the majority of data transactions there must be a wait state between the completion of one data tenure and the start of the next. This turnaround cycle avoids the contention on the data bus that would occur if one device starts driving data before another device has had a chance to turn off its data bus drivers. When a cache read hit is pipelined on top of another cache read hit, there is no need for this turnaround cycle since the same device will be driving the data bus for both data tenures. The 60X bus has the ability to remove this unnecessary wait state and allow back-to-back cache read hits to stream together. This ability is only enabled if the system is put into Fast L2 mode. Note that not all PowerPC processors support Fast L2 mode. One of the requirements for taking advantage of this data streaming capability is that the system arbiter must be sophisticated enough to identify situations in which streaming may occur. Upon recognizing these situations, it must assert the processor's data bus grant in the cycle coincident
MOTOROLA
MPC2605 11
with the fourth assertion of TA of the first cache read, so that the data tenure for the second cache read may commence in the next cycle. Because it only recognizes qualified assertions of CPU DBG, the MPC2605 must not be aware of the processor's assertions of DBB. This means that the DBB pin of the MPC2605 must be tied to a pullup resistor rather than connected to the system DBB to which all other devices are connected. This forces the system arbiter to a level of sophistication such that it only supplies qualified data bus grants and thus the DBB signal is unnecessary to the whole system. Note: In a multi-chip configuration each MPC2605 device acts as an independent cache. Zero wait state data streaming can only occur if the back to back read hits occur in a given device. If the second read hit is not in the device as the first read hit, a wait state will occur between the two data tenures (2-1-1-1-2-1-1-1 timing). Data Bus Parking The MPC2605 has the ability to respond to a processor read or write hit starting in the cycle after the processor has asserted TS. This is referred to as a 2-1-1-1 response. However, even though the MPC2605 has this ability, it is dependent upon the system to allow this quick of a response to occur. As discussed above, a data tenure cannot start until the master has been given a qualified bus grant. In order for the data tenure to start the cycle after TS is asserted, the data bus must be granted in the cycle coincident with the assertion of TS. At bus speeds of 66 MHz it is extremely difficult for an arbiter to detect an assertion of TS and itself assert CPU DBG in the same cycle. In order to realistically allow this situation to occur, CPU DBG must be asserted independent of the processor's assertion of TS. Data bus parking is a system feature whereby the processor always has a qualified data bus grant when the data bus is idle. It is also a requirement for systems which seek to take advantage of the 2-1-1-1 response time capabilities of the MPC2605. This feature is typically present in arbiters that have the level of sophistication necessary to support data streaming. But it is also a feature of systems that do not even have a data bus arbiter. In these systems the data bus grant of every device in the system is tied to ground. The assertion of DBB by the current data bus master effectively removes the qualified data bus grant of all devices in the system, including its own. Note that in systems that have no data bus arbiter that it is impossible to take advantage of data streaming. There is another caveat associated with data bus parking. Care must be taken when using data bus parking along with Fast L2 mode. In normal bus mode when the processor reads data off the bus, it will wait one cycle before passing the data on to internal functional units. The purpose of this one cycle waiting period is to check for an assertion of DRTRY, which invalidates the data that has been already read. One of the advantages of running the processor in Fast L2 mode is that this internal processor wait state is removed. A problem will arise, however, if the processor is given data the cycle after TS is asserted, as is possible with the MPC2605, and the transaction is aborted by some other device asserting ARTRY. Because the processor will not sam-
ple ARTRY until two cycles after the assertion of TS, the data read off the bus will have already been forwarded to the internal functional units. Thus, incorrect results may occur in the system. To avoid this situation in a system that seeks to run Fast L2 mode with the data bus parked, there must be a guarantee that ARTRY will never be asserted for cache read hits. This is a further requirement to be imposed upon the DMA bridge and the memory controller. If this guarantee cannot be made, the data bus cannot be parked when running in Fast L2 mode. Processor Reads When the processor issues a read transaction, the MPC2605 does a tag lookup to determine if this data is in the cache. If there is a cache hit and CI is not asserted, the MPC2605 will assert L2 CLAIM and supply the data to the processor when the data tenure starts. If the processor issues a cache-inhibited read (CI asserted) and the MPC2605 detects a cache hit to a non-dirty, or clean, cache line, the line will be marked invalid. If the cache-inhibited read hits a dirty line, the MPC2605 will assert ARTRY and write the dirty line back to memory. If the read misses in the cache, the MPC2605 will perform a linefill only if it is a burst read and it is not marked cache-inhibited. During a linefill, the MPC2605 stores the data present on the bus as it is supplied by the memory controller. Processor Writes The conditions for asserting L2 CLAIM for processor writes are almost the same as for processor reads. There must be a cache hit and CI must not be asserted. In addition, however, WT must not be asserted. Single beat writes that are marked either write-through or cache-inhibited that hit in the cache cause the MPC2605 to assert ARTRY and write the dirty line back to memory. Transaction Pipelining As explained in Pipeline Depth, the MPC2605 can only handle one level of pipelining on the bus. Since the assertion of L2 CLAIM gives it the ability to assert AACK, the MPC2605 has the ability to control this pipeline depth for transactions that are cache hits by delaying its assertion of AACK. Pipelined cache hits are transactions that hit in the cache but occur while there is still an outstanding data transaction on the bus. The timing of the assertion of AACK for a pipelined cache hit is dependent upon the completion of the previous transaction. For explanation purposes, the previous transaction will be referred to as transaction one. The pipelined cache hit will be referred to as transaction two. If transaction one is a cache hit, the MPC2605 will be the slave device for the transaction. Since, for burst operations, the MPC2605 always asserts TA for four consecutive clock cycles, the end of the data tenure for transaction one will be at a deterministic clock cycle. In this case, AACK for transaction two can be asserted coincident with the last assertion of TA for transaction one. If transaction one is not a cache hit, the MPC2605 will wait until after the data tenure for transaction one has completed before asserting AACK to complete the address tenure of transaction two.
MPC2605 12
MOTOROLA
MEMORY COHERENCE When a processor brings data into its on-chip cache and modifies it, a situation has arisen in which the main memory now contains irrelevant, or stale, data. Given that most systems support some form of DMA there must exist a means by which the processor is forced to write this modified, or dirty, data back to main memory. The DMA bridge is responsible for generating bus transactions to ensure that main memory locations accessed by DMA operations do not contain stale data. These transactions, called snoops, come in three different categories, each of which will be discussed below. Snoops cause the processor and the MPC2605 to check to see if they have dirty copies of the memory location specified in the snoop transaction. If either device does have a dirty copy it will assert ARTRY and make use of the opportunity presented in the BR window to write this data back to main memory. Situations can arise where a cache line is dirty in both the processor's L1 cache and in the MPC2605. In cases such as these, snoop transactions should cause the processor to write its data back to memory since it is by definition more recent than the data in the MPC2605. Since ARTRY is a shared signal and it cannot be determined which devices are driving it, the MPC2605 samples CPU BR in the BR window to determine if the snoop hit a dirty line in the L1 cache. If CPU BR is asserted during this window, the MPC2605 will defer to the processor. Snoop Reads A snoop read causes dirty data to be written back to memory but allows both the L1 and L2 to keep a valid copy. In cases where the snoop hits a dirty cache line in the processor, the MPC2605 will update its contents as the processor writes the data back to main memory. Snoop reads can be implemented in two ways. One is that the DMA bridge can issue a clean transaction (TT[0:4] = 00000). The other is that the DMA bridge can do a read transaction (TT[0:4] = x1010). If the DMA bridge does a read transaction, the MPC2605 determines that it is a snoop read rather than a processor read by the state of CPU BG the cycle before TS was asserted. If the processor was not granted the bus then the transaction had to have been issued by the DMA bridge and is therefore a snoop read. Snoop Writes Snoop writes also cause dirty data to be written back to main memory. The difference from a snoop read is that the cache line must then be invalidated in both the processor's cache and in the L2 cache. When the processor writes data back to memory in response to a snoop write, the MPC2605 will not cache the data as it appears on the bus. If a valid copy resides in the cache, the MPC2605 will invalidate it. Again there are multiple transactions that can be used by the DMA bridge to implement a snoop write. It can issue a flush transaction (TT[0:4] = 00100), a read with intent to modify (TT[0:4] = x1110), or a write with flush (TT[0:4] = 00010). As with snoop reads, the MPC2605 distinguishes between processor issued data transactions and snoop transactions by the state of CPU BG in the cycle previous to the assertion of TS.
Snoop Kills Kills are snoops that cause cache entries to be immediately invalidated, regardless of whether they are dirty. This saves time if the DMA operation is going to modify all the data in the cache line. To implement a snoop kill the DMA bridge can issue a kill transaction (TT[0:4] = 01100) or a write with kill (TT[0:4] = 00110). TWO/FOUR CHIP IMPLEMENTATION Multiple Castouts Because each MPC2605 has its own castout buffer (COB), it is possible for situations to arise in which more than one device needs to do a copyback operation. Under normal circumstances each device will enter castout conditions at different times. In these cases, when a device determines that it needs to do a castout, the L2 BR signal is first sampled. If L2 BR is already asserted then it is clear that another device is also in a castout situation. The late device will wait until L2 BR is negated before continuing in its attempt to perform its castout. Because of the BR window protocol associated with assertions of ARTRY, it is possible for a situation to arise where device two is waiting for device one to do its castout before asserting L2 BR. If there is an assertion of ARTRY by a device other than device one, device one is required to negate L2 BR in the BR window. In order to prevent device two from interpreting device one's negation of L2 BR as an indication that device one has completed its castout, a simple arbitration mechanism is used. All devices have a simple two-bit counter that is synchronized such that all counters always have the same value. For the purposes of performing a castout operation, a given pair can only assert L2 BR if the counter is equal to its value of CFG[1:2]. This simple mechanism prevents more than one device from asserting L2 BR in the same cycle and therefore not being cognizant of the another device's need to perform a castout. Snoop Hit Before Castout The other situation that can cause problems with a shared bus request occurs when a snoop hits a dirty line in one of the MPC2605 devices. If device one has a cache line in its COB, it will assert L2 BR so that it may perform a castout operation. If a snoop hits a dirty line in device two, it will assert both ARTRY and L2 BR so that it can write the snoop data back to main memory. When device one detects that ARTRY has been asserted, it needs to be made aware that device two needs to request the bus. Otherwise, at the same time that device two is asserting L2 BR, device one will attempt to conform to the BR window protocol and negate L2 BR. This situation is avoided by device one sampling FDN when it detects that ARTRY has been asserted. If FDN is asserted at the same time as ARTRY is asserted, device one will recognize that device two is asserting ARTRY. device one will then high-Z L2 BR so that there will not be contention when device two is asserting L2 BR. MULTIPROCESSING The MPC2605 can be used as a common cache for up to four processors. For each processor there is a bus request, bus grant, and data bus grant signal pin on the MPC2605. Each of these pins needs to be connected to the respective processor's arbitration signals in the system.
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MPC2605 13
The MPC2605 treats multiple processors as one processor. Thus, the same restrictions on pipelining depth are true with regard to how many processor transactions can be outstanding at any one time. There can only be one data transaction from ANY processor pipelined on top of a current data transaction that was issued by ANY processor. The data tenures for all processors must be performed in the same order as the address tenures on a system-wide basis. If processor one makes a request and then processor two makes a request, processor one's data tenure must precede processor two's data tenure. Note that this is not a 60X bus restriction, but rather a restriction necessary for proper operation of the MPC2605. The MPC2605 keeps coherent with the L1 caches of multiple processors as defined by the MESI (modified-exclusive- shared-invalid) protocol without actually implementing the protocol. This is possible for two reasons. Since the MPC2605 is a look-aside cache, all transactions are monitored by all devices on the bus. Also, the MPC2605 cannot, on its own, modify data. Thus, if one processor requests exclusive access to a cache line, it is not necessary for the MPC2605 to invalidate its copy of the data, as would be required under the MESI protocol. If a second processor requests the same data, the transaction will cause the first processor to assert ARTRY. This will prevent the MPC2605 from supplying stale data to the second processor. As discussed in Data Bus Parking, care must be taken when parking the data bus in Fast L2 mode. By the nature of MP systems running under the MESI protocol there will be assertions of ARTRY to abort cache read hits. Thus, in an MP system, the data bus cannot be parked to any processor if the system is to be run in Fast L2 mode. PWRDN An assertion of PWRDN will cause the MPC2605 to go into a low-power sleep state. This state is entered after PWRDN is synchronized and both the address and data buses are idle. All data is retained while in the sleep state. The behavior of the MPC2605 upon negation of PWRDN is dependent upon the state of WT at the rising edge of HRESET. If WT is asserted at reset, the MPC2605 will invalidate all cache entries when PWRDN is negated. If WT is negated at reset, the MPC2605 will leave all cache entries as they were prior to the assertion of PWRDN. However, in this situation, the system designer must insure that no bus activity occur within two microseconds of the negation of PWRDN. Note: While in the sleep state the MPC2605 does not disable its internal clock network. The low power state current stated in this specification assumes that the system clock is not toggling. ASYNCHRONOUS SIGNALS The MPC2605 supports four asynchronous control signals. These signals were originally defined in the PowerPC reference platform (PReP) specification. Because these signals are defined to be asynchronous, the MPC2605 must
synchronize them internally. This process takes eight clock cycles. Thus, to guarantee recognition by the MPC2605, assertions of any one of these signals must last a minimum of eight clock cycles. L2 FLUSH When L2 FLUSH is asserted, the MPC2605 initiates an internal sequence that steps through every cache line present. Valid lines that are clean are immediately marked invalid. Valid lines that are dirty must be written back to main memory. To keep memory up to date, the MPC2605 must still monitor all transactions on the bus. Any transaction that is not a processor burst write will cause the MPC2605 to assert ARTRY. Burst writes cause the MPC2605 to do a lookup on the affected address and mark the line invalid if it is present. Because the MPC2605 must still monitor all transactions, it cannot use the tag RAM for the flush sequence unless there is a guarantee that no new transaction will be initiated on the bus. The only way to ensure that no new transactions will occur is for the MPC2605 to be granted the bus. Thus, upon entering the sequence initiated by the assertion of L2 FLUSH, the MPC2605 will assert L2 BR. As soon as L2 BG is asserted, the MPC2605 can start stepping through the tag RAM entries. L2 FLUSH need not be held asserted for the flush sequence to complete. Once started the sequence will run to completion unless overridden by an assertion of HRESET. L2 MISS INH When L2 MISS INH is asserted, the MPC2605 will not load any new data into the cache. The data already present will remain valid and the MPC2605 will respond to cache hits. This condition only lasts as long as L2 MISS INH is asserted. When L2 MISS INH is negated, the MPC2605 will start to bring new data into the cache when there are cache misses. L2 TAG CLR When L2 TAG CLR is asserted, the MPC2605 will invalidate all entries in the cache. This internal sequence is the same as the one initiated by an assertion of HRESET. During this sequence, the MPC2605 will not participate in any bus transaction. However, it will keep track of all bus transactions so that when the sequence is finished, the MPC2605 can immediately participate in the next bus transaction. As is the case with assertions of L2 FLUSH, an assertion of L2 TAG CLR need not be held for the duration of the sequence. Once asserted the sequence will run to completion regardless of the state of L2 TAG CLR. L2 UPDATE INH When L2 UPDATE INH is asserted, the MPC2605 is disabled from responding to cacheable transactions. Bus transactions continue to be monitored so that as soon as L2 UPDATE INH is negated, the MPC204GA can participate in the next transaction.
MPC2605 14
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READ HIT/WRITE HIT Figure 1 shows a read hit from an idle bus state. The MPC2605 asserts L2 CLAIM the cycle after TS to inform the memory controller that there is a cache hit and the cache will control the rest of the transaction. L2 CLAIM is held through the cycle after AACK is asserted. Since there are no active data tenures from previous transactions, the MPC2605 asserts AACK the cycle after TS is asserted. Note there must be a qualified assertion of CPU DBG in the same cycle as the assertion of TS for the MPC2605 to respond with TA in the next cycle. CPU DBG does not affect the timing of L2 CLAIM or AACK. The write hit timing is virtually the same. The only difference is the processor drives the data instead of the MPC2605.
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LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High-Z
Figure 1. Burst Read (or Write) Hit
MOTOROLA
MPC2605 15
MULTIPLE READ/WRITE HITS (NORMAL BUS MODE) Figure 2 is an illustration of MPC2605 pipeline depth limit with multiple read hits. The MPC2605 supports only one level of address pipelining for data transfer. Therefore, it must hold off on its assertion of AACK for a pipelined TS until the data tenure for the first TS is done. The MPC2605 asserts AACK at the same time as the fourth TA for data tenures that it controls.
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LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High-Z
Figure 2. Multiple Burst Read (or Write) Hits
MPC2605 16
MOTOROLA
READ MISS (NORMAL BUS MODE) Figure 3 is an illustration of MPC2605 pipeline depth with a read miss followed by a read hit. For illustration purposes the read miss is shown as a 3-1-1-1 response from memory. AACK for the second access is not driven true until the cycle after the fourth TA of the read miss. This is because the MPC2605 is not in control of TA for the first access and must, therefore, wait until the first access' data tenure is complete before it can drive AACK true for the read hit.
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LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High-Z
Figure 3. Read Miss Followed by a Burst Read Hit for MPC603/604
MOTOROLA
MPC2605 17
MULTIPLE READ HITS (FAST L2 MODE) Back to back pipelined burst read hits for the MPC604 in Fast L2 mode, also called data streaming mode, are shown in Figure 4. Note that CPU DBG is negated except for the cycles coincident with the fourth TA of each data tenure. This is a requirement for data streaming. Note also that DBB is not shown. For proper operation in Fast L2 mode the DBB pin of the MPC2605 must be tied to a pull-up resistor.
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LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High-Z
Figure 4. Multiple Burst Read Hits in Fast L2 Mode
MPC2605 18
MOTOROLA
WRITE THROUGH BURST WRITE HIT Figure 5 shows the fastest possible burst write hit to a write-through mode L2 cache line, read miss or write miss processing that replaces a clean line. For these operations MPC2605 will not assert any signals on the 60X bus. A cache line is considered write through if WT is asserted by the processor when it asserts TS. The speed at which a write-through operation completes is solely dependent on the memory controller. The timing shown here assumes that the memory controller has a write buffer that can accept data this quickly.
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LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High-Z
Figure 5. Fastest Possible Write Through Burst Write Hit for MPC603/604
MOTOROLA
MPC2605 19
READ/WRITE MISS Figure 6 is an illustration of a processor read or write miss that causes the MPC2605 to replace a dirty line. L2 BR is asserted two clocks after TS. The dirty data to be replaced is moved into the internal cast out buffer (COB) at the same time the new data is written into the cache. Note that the copyback operation occurs after the processor request is satisfied. In addition, no delay is added to the processor transaction. It proceeds as fast as the memory controller will allow.
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Figure 6. Read or Write Miss Followed by Castout
MPC2605 20
MOTOROLA
READ/WRITE SNOOP HIT (DIRTY L2 LINE) Figure 7 is an illustration of a read or write snoop to a cache line that is dirty in the L2, but is not dirty in the processor's cache. When a snoop hits a dirty line, the MPC2605 will assert ARTRY through the cycle following the assertion of AACK. This cycle is called the ARTRY window. Note that the MPC2605 also asserts L2 BR at the same time it asserts ARTRY. Because the snoop could also have hit a dirty line in the processor's cache, the MPC2605 samples the processor's BR signal the cycle following the ARTRY window. This cycle is called the BR window. If the processor's BR signal is not asserted, the MPC2605 will start sampling L2 BG, the cycle after the BR window. Note that the MPC2605 cannot do a 2-1-1-1 copy back burst. The earliest that it can handle the first assertion of TA is two cycles after its assertion of TS.
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Figure 7. Read or Write Snoop Hit to Dirty L2 Cache Line and Clean Processor Cache Line
MOTOROLA
MPC2605 21
READ/WRITE SNOOP HIT (DIRTY L2 AND PROCESSOR LINE) An illustration of PowerPC read or write snoop hit to a dirty L2 cache line is shown in Figure 8. The processor has a dirty copy of the cache line. In this case, both the processor and the MPC2605 assert ARTRY. This situation is detected by sampling CPU BR in the BR window, as described in the previous example. If CPU BR is asserted in the BR window, the MPC2605 will negate L2 BR. It will also ignore assertions of L2 BG. This allows the processor to write back its dirty cache line, at which time the MPC2605 will either update or invalidate its copy depending on whether it is a snoop read or snoop write.
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LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High-Z
Figure 8. Read or Write Snoop Hit to Dirty L2 Cache Line and Dirty Processor Cache Line
MPC2605 22
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READ HIT/WRITE HIT (WITHOUT CPU DBG PARKED) Most of the previous examples have assumed CPU DBG is asserted in the same cycle that the processor asserts TS. This implies CPU DBG is parked. In some systems it may not be desirable or possible to park CPU DBG. Figure 9 shows the response for a read hit from the MPC2605 is gated by the assertion of CPU DBG. The fastest response possible in a system that does not park CPU DBG is 3-1-1-1.
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CPU DBG
DBB
TA DH0 - DH31, DL0 - DL31 LEGEND Signal driven to the MPC2605 Signal driven by the MPC2605 High-Z
A1
A2
A3
A4
Figure 9. Burst Read (or Write) Hit Without CPU DBG Parked
MOTOROLA
MPC2605 23
JTAG
AC OPERATING CONDITIONS AND CHARACTERISTICS FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TJ = 20 to + 110C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Termination to 1.5 V
TAP CONTROLLER TIMING
MPC2605-66 Parameter P Cycle Time Clock High Time Clock Low Time Clock Low to Output Valid Clock Low to Output High-Z Clock Low to Output Active Setup Times: Hold Times: TMS TDI TMS TDI Symbol S bl tCK tCKH tCKL tA tCKZ tCKX ts tsd th thd Min 30 12 12 5 0 0 2 2 Max -- -- -- 9 9 9 -- -- Unit Ui ns ns ns ns ns ns ns ns 2 3, 4 1 1 1 1 Notes N
NOTES: 1. This parameter is sampled and not 100% tested. 2. TDO will High-Z from a clock low edge depending on the current state of the TAP state machine. 3. TDO is active only in the SHIFT-IR and SHIFT-DR state of the TAP state machine. 4. Transition is measured 500 mV from steady-state voltage. This parameter is sampled and not 100% tested.
tCKH tCK TCK TEST CLOCK tS TMS TEST MODE SELECT tSD TDI TEST DATA IN tA TDO TEST DATA OUT tCKZ tCKX tHD tH tCKL
Figure 10. TAP Controller Timing
MPC2605 24
MOTOROLA
TEST ACCESS PORT DESCRIPTION
INSTRUCTION SET A five pin IEEE Standard 1149.1 Test Port (JTAG) is included on this device. When the TAP (Test Access Port) controller is in the SHIFT-IR state, the instruction register is placed between TDI and TDO. In this state, the desired instruction would be serially loaded through the TDI input. TRST resets the TAP controller to the test-logic reset state. The TAP instruction set for this device are as follows. STANDARD INSTRUCTIONS
Instruction BYPASS SAMPLE/PRELOAD EXTEST HIGHZ Code (Binary) 1111* 0010 0000 1001 Description Bypass instruction Sample and/or preload instruction Extest instruction High-Z all output pins while bypass register is between TDI and TDO Clamp output pins while bypass register is between TDI and TDO
pins. The EXTEST instruction would then be loaded. During EXTEST, the boundary-scan register is placed between TDI and TDO in the SHIFT-DR state of the TAP controller. Once the EXTEST instruction is loaded, the TAP controller would then be moved to the run-test/idle state. In this state, one cycle of TCK would cause the preloaded data on the output pins to be driven while the values on the input pins would be sampled. Note the TCK, not the clock pin (CLK), is used as the clock input while CLK is only sampled during EXTEST. After one clock cycle of TCK, the TAP controller would then be moved to the SHIFT-DR state where the sampled values would be shifted out of TDO (and new values would be shifted in TDI). These values would normally be compared to expected values to test for board connectivity. CLAMP TAP INSTRUCTION The CLAMP instruction is provided to allow the state of the signals driven from the output pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between TDI and TDO. The signals driven from the output pins will not change while the CLAMP instruction is selected. EXTEST could also be used for this purpose, but CLAMP shortens the board scan path by inserting only the bypass register between TDI and TDO. To use CLAMP, the SAMPLE/PRELOAD instruction would be used first to scan in the values that will be driven on the output pins when the CLAMP instruction is active. HIGHZ TAP INSTRUCTION The HIGH-Z instruction is provided to allow all the outputs to be placed in an inactive drive state (high-Z). During the HIGH-Z instruction the bypass register is connected between TDI and TDO. BYPASS TAP INSTRUCTION The BYPASS instruction is the default instruction loaded at power up. This instruction will place a single shift register between TDI and TDO during the SHIFT-DR state of the TAP controller. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. DISABLING THE TEST ACCESS PORT AND BOUNDARY SCAN It is possible to use this device without utilizing the four pins used for the test access port. To circuit disable the device, TCK must be tied to VSS to preclude mid level inputs. TRST should be tied to VSS to ensure proper HRESET operation. Although TDI and TMS are designed in such a way that an undriven input will produce a response equivalent to the application of a logic 1, it is still advisable to tie these inputs to VDD through a 1K resistor. TDO should remain unconnected.
CLAMP
1100
* Default state at power-up.
SAMPLE/PRELOAD TAP INSTRUCTION The SAMPLE/PRELOAD TAP instruction is used to allow scanning of the boundary-scan register without causing interference to the normal operation of the chip logic. The 169-bit boundary-scan register contains bits for all device signal and clock pins and associated control signals. This register is accessible when the SAMPLE/PRELOAD TAP instruction is loaded into the TAP instruction register in the SHIFT-IR state. When the TAP controller is then moved to the SHIFT-DR state, the boundary-scan register is placed between TDI and TDO. This scan register can then be used prior to the EXTEST instruction to preload the output pins with desired values so that these pins will drive the desired state when the EXTEST instruction is loaded. As data is written into TDI, data also streams out TDO which can be used to pre-sample the inputs and outputs. SAMPLE/PRELOAD would also be used prior to the CLAMP instruction to preload the values on the output pins that will be driven out when the CLAMP instruction is loaded. EXTEST TAP INSTRUCTION The EXTEST instruction is intended to be used in conjunction with the SAMPLE/PRELOAD instruction to assist in testing board level connectivity. Normally, the SAMPLE/ PRELOAD instruction would be used to preload all output
MOTOROLA
MPC2605 25
1
TEST-LOGIC RESET 0
0
RUN-TEST/ IDLE
1 SELECT DR-SCAN 1 0 1 1 0 SELECT IR-SCAN 1
CAPTURE-DR
CAPTURE-IR
0 SHIFT-DR 0
0 SHIFT-IR 0
1 EXIT1-DR 0 PAUSE 1-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 1
1 EXIT1-IR 0 PAUSE-IR 0 1
1 EXIT2-IR 1 UPDATE-IR 0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 11. TAP Controller State Diagram
MPC2605 26
MOTOROLA
BOUNDARY SCAN ORDER
BIT NUMBER The order of the boundary scan chain. Bit 0 is the closest to TDO. BIT/PIN NAME The name of the physical pin. For an output enable cell, this is the name of the corresponding output enable. BIT/PIN TYPE Input -- Input only pin. I/O -- Bi-directional pin that can be put into high-Z state. Output -- Output only pin. Output Enable -- Boundary scan cell to hold the output enable state of other I/O pads. Output enable does not correspond to a physical pin. To set an I/O to an input, the output enable must have a 1. To set an I/O to an output, the output enable must have a 0. Note that these internal output enables are active low. Reserved - This signal is reserved and must always be a 1. OUTPUT ENABLE The name of the output enable cell that determines if the cell is enabled or in the high-Z state. If the pin type is input or output enable, this entry will be empty.
Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Bit/Pin Type Reserved I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE Output Enable Bit Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Bit/Pin Name Reserved DL16 DL17 DL18 DL19 DL20 DL21 DL22 DL23 DP6 DL24 DL25 DL26 DL27 DL28 DL29 DL30 DL31 DP7 DH24 DH25 DH26 DH27 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Bit/Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O Input Input Input Input Input Input I/O Input I/O I/O Output Input I/O I/O I/O I/O Input Input Input I/O Input I/O I/O I/O AOE AOE AOE DBBOE AACKOE AOE ARTRYOE AOE L2BROE TAOE L2CLAIMOE FDNOE ABBOE Output Enable DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE
Bit/Pin Name DH28 DH29 DH30 DH31 DP3 DH16 DH17 DH18 DH19 DH20 DH21 DH22 DH23 DP2 L2 BG L2 MISS INH ABB CPU3 DBG CPU3 BG CPU3 BR CPU2 DBG CPU2 BG CPU2 BR FDN L2 DBG L2 BR TA L2 CLAIM CPU DBG AACK CI ARTRY WT CPU BR TEA PWRDN DBB HRESET TBST TT0 TS
MOTOROLA
MPC2605 27
Bit Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 79 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106
Bit/Pin Name TT1 TT2 TT4 TT3 CPU BG SRESET L2 TAG CLR L2 UPDATE INH CPU4 BG CPU4 DBG CPU4 BR CFG0 CFG2 CFG1 DH8 DH9 DH10 DH11 DH12 DH13 DH14 DH15 DP1 DH0 DH1 DH2 Dh3 DH4 DH5 DH6 DH7 DP0 DL0 DL1 DL2 DL3 DL4 DL5 DL6 DL7 DP4 DL8 DL9
Bit/Pin Type I/O I/O I/O I/O Input Input Input Input Input Input Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Output Enable AOE AOE AOE AOE
Bit Number 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Bit/Pin Name DL10 DL11 DL12 DL13 DL14 DL15 DP5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 TSIZ2 TSIZ0 TSIZ1 GBL
Bit/Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output
Output Enable DOE DOE DOE DOE DOE DOE DOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE
DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE DOE
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149
MPC2605 28
MOTOROLA
Bit Number 150 151 152 153 154 155 156 157 158 159 160
Bit/Pin Name CFG3 L2 CI L2 FLUSH AP0 AP1 AP2 AP3 APE TAOE L2CLAIMOE L2BROE
Bit/Pin Type Input Input Input I/O I/O I/O I/O Output Output Enable Output Enable Output Enable
Output Enable
Bit Number 161 162
Bit/Pin Name FDNOE DBBOE DOE ARTRYOE APEOE ABBOE AACKOE AOE
Bit/Pin Type Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
Output Enable
AOE AOE AOE AOE APEOE
163 164 165 166 167 168
ORDERING INFORMATION
(Order by Full Part Number) MPC
Motorola PowerPC Prefix Part Number
2605
ZP
66
X
Blank = Trays, R = Tape and Reel Speed (66 = 66 MHz) Package (ZP = PBGA)
Full Part Number -- MPC2605ZP66 MPC2605ZP66R
MOTOROLA
MPC2605 29
PACKAGE DIMENSIONS
ZP PACKAGE PBGA CASE 1138-01
4X
0.20 A C 0.20 C 0.25 C 0.35 C
D
E2
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM C. MILLIMETERS MIN MAX --- 2.05 0.50 0.70 0.95 1.35 0.70 0.90 0.60 0.90 25.00 BSC 22.86 BSC 22.40 22.60 1.27 BSC 25.00 BSC 22.86 BSC 22.40 22.60
D2 TOP VIEW D1
18X
B
e
DIM A A1 A2 A3 b D D1 D2 e E E1 E2
W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A2 A3 E1 A SIDE VIEW A1
241
b 0.03 0.15
M M
BOTTOM VIEW
CAB C
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
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MPC2605 30
MPC2605/D MOTOROLA

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